This invention relates to transistor logic circuits and more particularly to transistor flip-flop circuits utilizing so-called Emitter Function Logic (EFL) techniques.
Digital circuits using EFL techniques are known in the art. Such circuits are implemented with bipolar junction transistors and belong to the general class of Current Mode Logic (CML) circuits which also includes Emitter Coupled Logic (ECL) circuits. In general, CML circuits are capable of very high switching speeds, however, for a number of logic functions EFL circuits are known to have lower power-delay products and greater packing density in an integrated circuit than ECL circuits.
The basic EFL gate, which typically comprises a pair of multi-emitter transistors and a pull-up resistor, provides the AND-OR logic function. The basic EFL latch circuit is formed by connecting together one emitter of each transistor in a basic EFL gate. A description of the basic EFL gate and the basic EFL latch is contained in U.S. Pat. No. 3,795,822, issued to Z. E. Skokan on Mar. 5, 1974 and entitled Multi-Emitter Coupled Logic Gate.
Complex logic functions are achieved in EFL circuits by combining the basic EFL gate or the basic EFL latch with a multi-level current steering network of the type commonly used in ECL circuits. Examples of circuits which combine the basic EFL latch with a one level current steering network is described in a paper by Z. E. Skokan, entitled Emitter Function Logic Family for LSI published in the IEEE Journal of Solid State Circuits in October 1973 on pages 356 to 361. Examples of circuits which combine the basic EFL latch with a two level current steering network is described in a paper by J. Kane entitled "A Low-Power, Bipolar, Two's Complement Serial Pipeline Multiplier Chip" published in the IEEE Journal of Solid State Circuits in October, 1976 on pages 669 to 678.
One problem with the EFL circuit technique is that the highly important J-K flip-flop function is difficult to implement. The logical structure of the J-K flip-flop normally requires the feedback of both the true and complement outputs of the slave latch to an input logic circuit which provides data to the master latch. Since the basic EFL latch circuit does not provide both true and complement outputs, the J-K flip-flop cannot be implemented without resorting to complex circuit techniques which degrade performance, increase power dissipation and enlarge chip layout area when used in an integrated circuit.
A prior art solution to the problem of implementing the J-K flip-flop in EFL is described in U.S. Pat. No. 4,145,623, issued to R. L. Doucette on Mar. 20, 1979 and entitled "Current Mode Logic Compatible Emitter Function Type Logic Family". The Doucette solution requires modification of the basic EFL latch to provide both true and complement outputs. However, these modifications increase the parasitic capacitances at sensitive timing nodes of the latch circuit and thus significantly degrade the performance of the flip-flop circuit in which it is used.
Therefore, a need clearly exists for an EFL J-K flip-flop circuit which does not require modification of the basic EFL latch circuit nor the feedback of both true and complement outputs and which has high performance, low power dissipation and small layout area in an integrated circuit.